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The CD54HCT161 is obsolete and no longer is supplied. Data sheet acquired from Harris Semiconductor SCHS154D
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
High-Speed CMOS Logic Presettable Counters
Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the 'HC161 and 'HCT161 types). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.
February 1998 - Revised October 2003
Features [ /Title (CD74 HC161 , CD74 HCT16 1, CD74 HC163 , CD74 HCT16 3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed
* 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset * 'HC163, 'HCT163 4-Bit Binary Counter, Synchronous Reset * Synchronous Counting and Loading * Two Count Enable Inputs for n-Bit Cascading * Look-Ahead Carry for High-Speed Counting * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD54HC161F3A CD54HC163F3A CD54HCT163F3A CD74HC161E CD74HC161M CD74HC161MT CD74HC161M96 CD74HC163E CD74HC163M CD74HC163MT CD74HC163M96 CD74HCT161E CD74HCT161M CD74HCT161MT CD74HCT161M96 CD74HCT163E CD74HCT163M CD74HCT163MT CD74HCT163M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Description
The 'HC161, 'HCT161, 'HC163, and 'HCT163 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The 'HC161 and 'HCT161 are asynchronous reset decade and binary counters, respectively; the 'HC163 and 'HCT163 devices are decade and binary counters, respectively, that are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met). All counters are reset with a low level on the Master Reset input, MR. In the 'HC163 and 'HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met.
NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2003, Texas Instruments Incorporated
1
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Pinout
CD54HC161, CD54HCT161, CD54HC163, CD54HCT163 (CERDIP) CD74HC161, CD74HCT161, CD74HC163, CD74HCT163 (PDIP, SOIC) TOP VIEW
MR 1 CP 2 P0 3 P1 4 P2 5 P3 6 PE 7 GND 8 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE
Functional Diagram
P0 3 SPE CP MR PE TE 9 2 1 7 10 4 P1 5 P2 6 14 13 12 11 15 Q0 Q1 Q2 Q3 TC P3
2
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
MODE SELECT - FUNCTION TABLE FOR 'HC161 AND 'HCT161 INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count Inhibit H H H CP X X X PE X X X h I (Note 2) X TE X X X h X I (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) Pn X l h X X X OUTPUTS Qn L L H Count qn qn TC L L (Note 1) (Note 1) (Note 1) L
MODE SELECT - FUNCTION TABLE FOR 'HC163 AND 'HCT163 INPUTS OPERATING MODE Reset (Clear) Parallel Load MR l h (Note 3) h (Note 3) Count Inhibit h (Note 3) h (Note 3) h (Note 3) CP X X PE X X X h I (Note 2) X TE X X X h X I (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) Pn X l h X X X OUTPUTS Qn L L H Count qn qn TC L L (Note 1) (Note 1) (Note 1) L
H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don't Care; q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition; = Low-to-High clock transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for HC/HCT161 and 'HC/HCT163). 2. The High-to-Low transition of PE or TE on the 'HC/HCT161 and the 'HC/HCT163 should only occur while CP is HIGH for conventional operation. 3. The Low-to-High transition of SPE on the 'HC/HCT161 and SPE or MR on the 'HC/HCT163 should only occur while CP is HIGH for conventional operation.
3
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 4. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 5) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS A
VCC (V) 6
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
100
0.1 8 360
-
1 80 450
-
1 160 490
A A A
HCT Input Loading Table
INPUT P0 - P3 PE CP MR SPE TE UNIT LOADS 0.25 0.65 1.05 0.8 0.5 1.05
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC.
5
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Prerequisite For Switching Specifications
PARAMETER HC TYPES Maximum CP Frequency (Note 6) fMAX 2 4.5 6 CP Width (Low) tW(L) 2 4.5 6 MR Pulse Width (161) tW 2 4.5 6 Setup Time, Pn to CP tSU 2 4.5 6 Setup Time, PE or TE to CP tSU 2 4.5 6 Setup Time, SPE to CP tSU 2 4.5 6 Setup Time, MR to CP (163) tSU 2 4.5 6 Hold Time, PN to CP tH 2 4.5 6 Hold Time, TE or PE to CP tH 2 4.5 6 Hold Time, SPE to CP tH 2 4.5 6 Recovery Time, MR to CP (161) tREC 2 4.5 6 6 30 35 80 16 14 100 20 17 60 12 10 50 10 9 60 12 10 65 13 11 3 3 3 0 0 0 0 0 0 75 15 13 5 24 28 100 20 17 125 25 21 75 15 13 65 13 11 75 15 13 80 16 14 3 3 3 0 0 0 0 0 0 95 19 16 4 20 24 120 24 20 150 30 26 90 18 15 75 15 13 90 18 15 100 20 17 3 3 3 0 0 0 0 0 0 110 22 19 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
6
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Prerequisite For Switching Specifications
PARAMETER HCT TYPES Maximum CP Frequency CP Width (Low) (Note 6) MR Pulse Width (161) Setup Time, Pn to CP Setup Time, PE or TE to CP Setup Time, SPE to CP Setup Time, MR to CP (163) Hold Time, PN to CP Hold Time, TE or PE to CP Hold Time, SPE to CP Recovery Time, MR to CP (161) NOTE: 6. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC devices: 1 1 f MAX (CP) = ----------------------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------- 21MHz ( min ) CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold 37 + 10 + 0 fMAX tW(L) tW tSU tSU tSU tSU tH tH tH tREC 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 30 16 20 10 13 12 13 5 3 3 15 24 20 25 13 16 15 16 5 3 3 19 20 24 30 15 20 18 20 5 3 3 22 MHz ns ns ns ns ns ns ns ns ns ns SYMBOL (Continued) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
TEST CONDITIONS
Switching Specifications
CL = 50pF, Input tr, tf = 6ns 25oC -40oC TO 85oC MAX MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay CP to TC
SYMBOL
TEST CONDITIONS
VCC (V)
MIN
TYP
tPHL, tPLH
CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 15 15 9 185 37 31 185 37 31 120 24 20 230 46 39 230 46 39 150 30 26 280 56 48 280 56 48 180 36 31 ns ns ns ns ns ns ns ns ns ns ns ns
CP to Qn
tPHL, tPLH
CL = 50pF
TE to TC
tPHL, tPLH
CL = 50pF
7
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued) 25oC PARAMETER MR to Qn (161) SYMBOL tPHL TEST CONDITIONS CL = 50pF VCC (V) 2 4.5 CL = 15pF CL = 50pF MR to TC (161) tPHL CL = 50pF 5 6 2 4.5 CL = 50pF Output Transition Time tTHL, tTLH CL = 50pF 6 2 4.5 6 Power Dissipation Capacitance (Notes 7, 8) Input Capacitance HCT TYPES Propagation Delay CP to TC tPHL, tPLH CL = 50pF CL = 15pF CP to Qn tPHL, tPLH CL = 50pF CL = 15pF TE to TC tPHL, tPLH CL = 50pF CL = 15pF MR to Qn (161) tPHL CL = 50pF CL = 15pF MR to TC (161) Output Transition Time Power Dissipation Capacitance (Notes 7, 8) Input Capacitance NOTES: 7. CPD is used to determine the dynamic power consumption, per package. 8. PD = CPD VCC2 fi + (CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. tPHL tTHL, tTLH CPD CIN CL = 50pF CL = 50pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 4.5 5 18 16 13 21 63 42 39 32 50 50 15 53 49 40 63 63 19 63 59 48 75 75 22 ns ns ns ns ns ns ns ns ns ns pF CPD CIN 5 MIN TYP 18 60 MAX 210 42 36 210 42 36 75 15 13 -40oC TO 85oC MIN MAX 265 53 45 265 53 45 95 19 16 -55oC TO 125oC MIN MAX 315 63 54 315 63 54 110 22 19 UNITS ns ns ns ns ns ns ns ns ns ns pF
CL = 50pF
-
10
-
10
-
10
-
10
pF
CL = 50pF
-
10
-
10
-
10
-
10
pF
8
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Timing Diagram
MASTER RESET (161) MASTER RESET (163) SPE (ASYNCHRONOUS) (SYNCHRONOUS)
P0 PRESET DATA INPUTS P1 P2 P3 CP (161) CP (163) PE TE Q0 Q1 OUTPUTS Q2 Q3 TC 12 RESET PRESET 13 14 15 0 1 2 INHIBIT
COUNT ENABLES
COUNT
Sequence illustrated on waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit.
9
CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 Test Circuits and Waveforms
trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
tr = 6ns INPUT 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V
GND tTHL
GND
tTHL
INVERTING OUTPUT
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL CLOCK INPUT 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT
trCL 2.7V 0.3V tH(H)
tfCL 3V 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 90% 1.3V 10% tPHL GND
DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL
50% GND
OUTPUT
90% 1.3V tPLH
50% GND
tREM 3V SET, RESET OR PRESET
1.3V GND
IC
CL 50pF
IC
CL 50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
10
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device CD54HC161F CD54HC161F3A CD54HC163F3A CD54HCT161F3A CD54HCT163F CD54HCT163F3A CD74HC161E CD74HC161M CD74HC161M96 CD74HC161MT CD74HC163E CD74HC163M CD74HC163M96 CD74HC163MT CD74HCT161E CD74HCT161M CD74HCT161M96 CD74HCT161MT CD74HCT163E CD74HCT163M CD74HCT163M96 CD74HCT163MT
(1)
Status (1) ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP CDIP CDIP CDIP CDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC
Package Drawing J J J J J J N D D D N D D D N D D D N D D D
Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1 1 25 40 2500 250 25 40 2500 250 25 40 2500 250 25 40 2500 250 1 1 1 None None None None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish Call TI Call TI Call TI Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Call TI Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free).
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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